The invention relates to a method for producing chip packages, and to a chip package produced in this way.
In a conventional packaging process for semiconductor chips, the chips are packaged separately after the sawing of the semiconductor wafer. By contrast, in wafer level packaging, the semiconductor chips of a wafer are packaged at the wafer level. For this purpose, by using a thin-film technology, pads of the chips are rewired in one or a plurality of overlying metallization layers and contacts are applied in the form of solder balls for contact-connecting the finished wafer level package to the printed circuit board. In this case, the basic area of the wafer level packages corresponds, in principle, to the chip area of the semiconductor chips.
By comparison with conventional wafer level packages, fan-out wafer level packages have a basic area that is greater than the chip area, with the result that a larger basic area is available for contact-connecting the finished packages to the printed circuit board.
Packages of this type are often produced in such a way that firstly a semiconductor wafer is sawn. After the sawing individual chips are arranged alongside one another on a carrier device with a larger distance between them in comparison with the distance on the wafer. This is typically done by using an automatic pick-and-place machine that takes the individual chips from the sawn wafer assembly and positions them onto a carrier device. The chips are subsequently encapsulated into e.g., mould compound, thereby giving rise to a reconstituted wafer composed of mould compound with embedded semiconductor chips. Using a thin-film technology applied to the cured reconstituted wafer, the pads of the chips are rewired in overlying layers and solder balls for contact-connecting the finished wafer lever package to the printed circuit board are applied. For this purpose, the wafer has to be exposed by using a mask aliner or a stepper. Since the positioning and orientation of the chips on the carrier device can only be effected with a limited accuracy and additional inaccuracies with regard to the positioning and orientation of the chips also occur in the subsequent processes, the linking of, in particular, small and/or closely spaced-apart pads in the context of the rewiring is critical. Thus, short circuits between two pads or non-linking of individual pads can occur as a result of an incorrect positioning and/or rotation during the rewiring. This regularly leads to the failure of the affected component. Defects of this type are to be expected to an increasing degree in the future since the pad size and the pad pitch (distance between the mid points of two adjacent pads) will decrease further while the wafer or panel sizes (panel size=number of chips packaged simultaneously in a method sequence) in the context of packaging will, however, increase further.
For these and other reasons, there is a need for the present invention.